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makefile: Use $(MAKE) (#71) 

This software requires GNU make to build, which is installed as "gmake"
on *BSD.  Therefore, use $(MAKE) to make sure that the same GNU make is
invoked to build the sub-project.
This commit is contained in:
Aaron LI 2018-10-05 23:22:27 +08:00 committed by Cylgom
parent dcd0aa6de2
commit 04580c6ff0
1 changed files with 2 additions and 2 deletions
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makefile
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@ -41,7 +41,7 @@ $(OBJD)/%.o:%.c
$(SUBD)/termbox-next/bin/termbox.a: $(SUBD)/termbox-next/bin/termbox.a:
@echo "building static object $@" @echo "building static object $@"
@cd $(SUBD)/termbox-next && make @(cd $(SUBD)/termbox-next && $(MAKE))
$(BIND)/$(NAME):$(OBJS) $(BIND)/$(NAME):$(OBJS)
@echo "compiling $@" @echo "compiling $@"
@ -74,4 +74,4 @@ clean:
@echo "cleaning workspace" @echo "cleaning workspace"
@rm -rf $(BIND) @rm -rf $(BIND)
@rm -rf $(OBJD) @rm -rf $(OBJD)
@(cd $(SUBD)/termbox-next && make clean) @(cd $(SUBD)/termbox-next && $(MAKE) clean)