67 lines
1.0 KiB
Makefile
67 lines
1.0 KiB
Makefile
# Standard variables and targets for projects.
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ifeq (,$(MAKEFILE_PROJECT_VARS))
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MAKEFILE_PROJECT_VARS = TRUE
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# Guarantee these are all empty (we don't want a conflict with any env vars)
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LIBS :=
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INCLUDE :=
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BINS :=
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SCRIPTS :=
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SS :=
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STK :=
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MODELS :=
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ETC :=
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DOC :=
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MAN :=
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FONTS :=
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ICONS :=
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APPDEFAULTS :=
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TCL :=
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TELEUSE :=
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SHADERS :=
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ifeq (,$(MAKEFILE_PENV_VARS))
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include $(DTOOL)/include/Makefile.penv.vars
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endif
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ifeq (,$(CTPROJECT))
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CTPROJECT = project
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endif
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ifeq (,$(CTPROJROOT))
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CTPROJROOT := $(shell $(DTOOL)/bin/ctproj -r)
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endif
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ifneq (,$(OPTIMIZE))
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export OPTIMIZE
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endif
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install: install-$(CTPROJECT)
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uninstall: uninstall-$(CTPROJECT)
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clean: clean-$(CTPROJECT)
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cleanall: cleanall-$(CTPROJECT)
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touch: touch-$(CTPROJECT)
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copy: copy-$(CTPROJECT)
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isinstalled: isinstalled-$(CTPROJECT)
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notinstalled: notinstalled-$(CTPROJECT)
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checkinstall: checkinstall-$(CTPROJECT)
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toinstall: toinstall-$(CTPROJECT)
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depends: depends-$(CTPROJECT)
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nodepends: nodepends-$(CTPROJECT)
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showuses: showuses-$(CTPROJECT)
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endif # MAKEFILE_PROJECT_VARS
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